MOS dynamic random access memories (RAMS) have provided the lowest cost semiconductor memory storage yet achievable. Recent research in the area of MOS dynamic RAMS has led to steadily increasing bit density and faster access times. However, as the density of storage cells of an MOS array has in-increased, the size of the individual cells has become progressively smaller and the current discharging capability of the individual storage cells with respect to discharging the bit sense line capacitance is decreased. Efforts have been made to increase the access times of dynamic MOS memories by providing circuits which sense small voltage changes of the bit sense line. Another approach has been to couple the bit sense line to a circuit which senses the initial discharge of the bit sense line by a storage cell and cuts in to rapidly complete the discharge thereof. Dynamic latch circuits have been used to accomplish this purpose. However, such dynamic latch circuits have had the disadvantage that they provide a rather low impedance connected to the bit sense line during a write cycle and do not permit a read-modifywrite cycle. This is because the output of the dynamic latch is disabled or set to a high impedance state by a clock signal used for precharging various nodes of the memory prior to the read clock signal. During the read or refresh portion of a memory cycle, however, the state of the speed-up latch may be switched, resulting in a low output impedance during a following write operation. Conventional bootstrap circuit, which could be used on the latch circuit, dissipate a substantial amount of power.